Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft is seeking a highly motivated, FPGA and ASIC IP design engineering manager to build innovative FPGA-based computing systems within a large design team. Well-designed hardware can deliver huge amounts of fine-grained parallelism and, therefore, significantly accelerate many types of computations as well as provide very fast infrastructure. Microsoft provides a great channel for product impact that touches the lives of millions of users daily, in an environment at the cutting edge of high-performance computing.
Seeking a personable, energetic candidate to build the automated validation self-checking suite embedded in FPGA designs. The target designs will focus on developing an FPGA Shell (hardware abstraction layer) on FPGAs for Microsoft's next generation of cloud servers and applications. A strong candidate will be creative, think critically, able to analyze & resolve complex issues and have strong communications skills. Technical experience in design verification, RTL base design and emulation or FPGA synthesizable testbenches are a plus.
rimary responsibilities include:
- Collaborate with application groups to define and architect validation solutions that meet system coverage goals.
- Develop, simulate, verify and validate RTL and HLS based designs through industry standard FPGA development flows.
- Contribute to evaluation, selection and integration of 3rd party IP blocks in FPGA and ASIC solutions.
- Work with a team of hardware and software engineers to deploy highly reliable solutions to a very large user base.
- A solid electrical and/or computer engineering background (MS in electrical and/or computer engineering or equivalent degree preferred, BS required).
- At least three years of verification experience in self-checking testbench, coverage driven and UVM base projects.
- RTL coding design expertise using Verilog, System Verilog.
- Experience or knowledge of synthesizable testbench on FPGA or emulation platforms (Palladium, Zebu).
- Experience working in a team environment.
Desired skills and experience:
- Experience in compilation flows and/or FPGA CAD tool development a plus.
- FPGA design, implementation and tool flow expertise, including HLS development
- Programming and scripting in C, C++, C#, OpenCL, System C, Powershell, TCL and/or Perl
- Knowledge of Windows device driver hardware interfaces
Position requires limited domestic and international travel
Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge cloud technology that changes our world. The Cloud Hardware Infrastructure Engineering (CHIE) team in Microsoft's Azure C+E division is responsible for delivering server infrastructure for Microsoft's online services. The hardware for operating these services (over 200 and counting), comprises of hundreds of thousands of servers spread globally and applications that reach hundreds of millions of users every day. Our customer-base is growing rapidly, our infrastructure investments are multiplying, and the size of our global infrastructure is increasing by the day - along with the scale of our challenges. Learn more about our team and projects here Azure Hardware Infrastructure
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.
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