Principal System On Chip Integration Engineer

Microsoft’s hardware teams incubate advanced technologies and build deep partnerships with internal research, product planning, and marketing teams. Microsoft ships tens of millions of hardware products every year, including the Xbox, Surface devices, HoloLens, accessories, and much more. Our opportunities represent a variety of disciplines including, but not limited to, design, verification, performance modeling and DevOps supporting the development of custom silicon. The Silicon Computing Development Team is seeking passionate, driven, and intellectually curious Principal System On Chip Integration Engineer to deliver premium-quality designs once considered impossible. Our team is involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems ranging from traditional computing solutions to artificial intelligence and augmented reality. We are responsible for delivering cutting-edge, custom central Central processing unit (CPU) and System On Chip (SOC) designs that can perform complex and high-performance functions in an extremely efficient manner.Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.Embody our Culture and ValuesRequired/Minimum Qualifications9+ years of related technical engineering experienceOR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experienceOR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experienceOR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.8+ years of experience in design flows and methodologies including Lint, CDC, RDC, synthesis, timing, and power analysis 5+ years of technical experience in SOC Integration.Experience in delivery of ASIC IPs, sub-systems and/or top level SOC RTL for 3+ tape outs.Other RequirementsAbility to meet Microsoft, customer and/or government security screening reqirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.Additional or Preferred Qualifications15+ years technical engineering experienceOR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experienceOR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experienceOR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience.Proven track record of silicon delivery as a team leader.Demonstrated expertise in Computer Architecture, Digital Design, IP and SOC development.Experience with front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power intent, linting, Synthesis, STA).Experience in designing for testability, debug, and manufacturing.Ability to write scripts using Python, Perl, Tcl, etc.Expertise in industry standard tools used for design abstraction, integration, and wiring. Expertise in front end design flows and methodologies: SCM, RTL partitioning, third party IP integration, synthesis, memory map, and 1st order verification debug. Understanding in clock crossing techniques.Domain knowledge in one or more of these areas is a plus: PCIe, Fabric, Security, CPU, Coherence, high speed interfaces/protocols. Expertise with industry standard RTL tools and flows.Highly proficient in Verilog/System Verilog. Experience in high performance and low power design techniques.Understanding of IP development & SOC integration challenges at subsystem and full chip level. Experience with clock/reset design. Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $133,600 - $256,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $173,200 - $282,200 per year.Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.  We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.Lead SOC implementation and integration strategies.Collaborate with SOC Integration and Intellectual Property (IP) Design Engineers to ensure Register Transfer Level (RTL) quality and timeliness.Continuously evaluate and refine implementation for area, power, and performance optimization.Efficiently integrate diverse functional blocks into the SOC architecture.Conduct comprehensive functionality testing of blocks, including basic tests and debugging for various features at both IP and SOC levels as required.Perform design quality checks such as Lint, CDC, RDC, and Low Power Intent analysis.Coordinate closely with the verification team to ensure overall design quality.Provide mentorship and guidance to junior engineers.Promote a growth mindset by challenging the status quo.Employment typeFull-TimeWork siteUp to 50% work from homeRole typeIndividual ContributorDisciplineSilicon EngineeringProfessionHardware Engineering