Senior FPGA Engineer
| Verified Pay check_circle | Provided by the employer$215000 - $250000 per year |
|---|---|
| Hours | Full-time |
| Location | Redmond, WA Redmond, Washington open_in_new |
About this job
Job Description
Kapta Space is seeking a Senior FPGA Engineer to lead RTL design and FPGA development for radar operation and algorithm implementation. Kapta Space is seeking FPGA Engineers with experience in mission-critical firmware development that have the drive and experience to complete projects independently and on time.
- Assist multi-disciplinary team in creating firmware requirements
- Architect, design, and implement software for our Radar Sensor
- Work collaboratively with radar algorithm, hardware, software and mechanical engineers to build reliable, embedded firmware for the payload
- Evaluate implementation/maintenance, complexity and resource requirements (logic cells, embedded memory, DSP Slices) for control and signal processing routines in RTL. Produce trade-studies to support decision making
- Integrate RTL designs onto FPGA/SoC platforms with synthesis, place and route, and timing analysis
- Lead verification and validation of FPGA design on prototype and fight hardware
- Assist in recruiting, interviewing, and hiring additional teammates to our rapidly growing team
- BS or MS degree in Electrical Engineering, Computer Engineering, or related field
- 8+ years of experience in embedded firmware development (ideally for radar applications)
- Experience with bring up and verification of RTL-based designs on targeted HW
- Experience with low-speed interfaces (I2C, SPI, UART, RS422, etc.)
- Comfortable with Git, CI, Code Reviews, and Version Control and organized enough to be productive in a lean startup environment
- Experience in RTL design with Verilog/VHDL for satellite applications
- Ability to read schematic diagrams
- Don’t meet them all? Not a problem. Please apply even if you do not meet all these criteria.
- Experience designing and implementing distributed digital systems
- Experience with Clock Domain Crossing and Timing Closure
- Experience with AMD Ultrascale+ platforms
- Experience with interfaces for high-speed ADC/DACs (JESD204)
- Experience implementing signal processing algorithms in RTL
- Experience with embedded designs with multiple FPGAs and peripheral interfaces (SPI, UART, GPIO, I2C, Ethernet)
- Experience implementing efficient, low latency data movement between FPGAs, processors, storage devices, and networking interfaces
- Working knowledge of networking stacks (Ethernet, TCP/IP)
- Ability to gain and hold a TS security clearance
Concerned you do not meet all the requirements? Not a problem - please apply even if you do not meet all these criteria.
The estimated salary range for this role reflects base pay only and is influenced by a variety of factors. Actual offers may vary based on factors including, but not limited to, a candidate's experience, education or training, specialized expertise, and the needs of the business. In addition to base pay, full-time roles include competitive equity grants that reward innovation, impact, and long-term growth. Our total compensation philosophy is designed to recognize excellence while fostering a culture of collaboration, curiosity, and shared success.
We may use artificial intelligence (AI) tools to assist our recruitment team but do not replace human judgment. All final hiring decisions are made by humans.