Macpower Digital Assets Edge Private Limited Principal Design Verification Engineer - UAL & PCIe Subsystems SME in Santa Clara, CA | 1309829037

Verified Pay check_circle	$158600 - $317800 per year
Hours	Full-time
Location	Santa Clara, CA Santa Clara, California open_in_new

About the Role & Team:

As part of the Design Verification Engineering Team, you will verify the critical circuitry inside our chips for the general market and specific tier-one customers. These chips utilize cutting-edge technology to facilitate high-speed data transfers. You will play a vital role in ensuring each design meets stringent customer specifications across major telecom, automotive, and technology sectors.
In this role, you will develop the architecture for functional verification environments including reference models and bus-functional monitors and drivers and actively contribute to the underlying verification methodologies.

Key Responsibilities:

Test Planning & Development: Write detailed verification test plans using random techniques and coverage analysis; collaborate with design teams to ensure plan completeness.
Environment Optimization: Develop targeted tests and tune the verification environment to successfully achieve coverage goals.
Debugging: Debug test failures and work directly with designers to resolve underlying chip issues.
Firmware & Multi-Core Tooling: Verify boot code and architect, develop, and maintain software tools that streamline the design of state-of-the-art multi-core SoCs.
Scalable Software Engineering: Transform engineering requirements into highly parallel, scalable, and user-friendly software infrastructure tools.
Software QA: Perform comprehensive unit and regression testing of internal software tools.

Position Requirements:
Education & Experience:

Education: BS, MS, or PhD in Computer Science, Electrical Engineering, or Computer Engineering.
Experience: 10 12 years of relevant professional experience in hardware verification and software/firmware development.

Required Technical Skills:

Methodologies: Strong proficiency with SystemVerilog and UVM.
Environment Building: Proven experience writing detailed test plans and building sophisticated, directed, and constrained-random verification environments.
Protocols: Prior working knowledge of UAL or PCIe protocols.
Scripting & EDA: Experience with scripting languages like Python or Perl alongside industry-standard EDA verification tools.
Software Design: Experience with Object-Oriented Design (OOD) and implementation.
Operating Systems: Good technical understanding of the Linux OS.
Programming: Solid programming skills, specifically in C and ARM assembly.

Professional & Soft Skills:

Diligent, detail-oriented, and highly proactive with the ability to handle complex assignments with minimal supervision.
Collaborative mindset with the ability to accept, process, and work with differing engineering opinions (must be an open-minded developer).
Dynamic learner who can adapt quickly on the fly within a fast-paced environment.

Principal Design Verification Engineer - UAL & PCIe Subsystems SME