Hardware Design Engineer 4

THE ROLE:
As a member of the CT Server DDR team, we are looking for an experienced signal integrity and power integrity engineer who can be responsible for DDR PHY channel and power delivery network (PDN) architecture, system-level SI/PI, and post-silicon validation.

THE PERSON:
The engineer needs to be hands-on in defining channel and PDN architectures, modeling signal and power delivery at the system level, and validating SI/PI on silicon. The engineer needs to work with design, package, board, and firmware teams on the specification of SI/PI targets and their implementation, and to help debug issues across the full system stack.

KEY RESPONSIBILITIES:
Run system-level channel and PDN simulations (insertion/return loss, crosstalk, eye diagrams, impedance, IR drop, jitter transfer) and correlate with silicon results
Able to process post-silicon SI/PI validation data and drive the next steps
Debug SI/PI issues across silicon, package, and board, working with firmware and design teams
Support cross-functional teams with system, channel, PDN, and decoupling implementation details

PREFERRED EXPERIENCE:
Strong coding skills in Python and Matlab preferred
Signal integrity (SI) and power integrity (PI) knowledge, including S-parameter/Z-parameter analysis, channel modeling, and PDN modeling
Knowledge of Ansys or Cadence simulation tools (e.g., HFSS, SIwave, Sigrity, Clarity)
System-level experience with firmware and hardware debug expertise preferred
System modeling with silicon-to-simulation correlation
Firmware development for ATE and platforms

ACADEMIC CREDENTIALS:
Bachelors or Masters degree in Computer Engineering/Electrical Engineering

LOCATION: Santa Clara, CA (Open to other *** locations)