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Job Description

Job Description
Required Technical Skills:
  • 5 years of hands-on experience in Design for Test (DFT) and Automatic Test Pattern Generation (ATPG) for SoC or ASIC designs.
  • Strong understanding of DFT fundamentals, including controllability, observability, and scan-based testing.
  • Proven expertise in ATPG pattern generation, analysis, and debugging.
  • Experience with MBIST, including memory test architectures and diagnostics.
  • Knowledge of I/O test methodologies for interface-level and pin-level validation.
  • Solid understanding of clock DFT and clock verification concepts.
  • Strong knowledge of digital design and RTL fundamentals.
  • Experience with industry-standard DFT/ATPG EDA tools.
  • Ability to work effectively in fast-paced, high-performance semiconductor programs.
  • Strong analytical, problem-solving, and communication skills.

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Posting ID: 1311865497 Posted: 2026-11-08 Job Title: Engineer