Principal Engineer, Project Coordinator

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.

What You Can Expect

ASIC design engineer responsible for planning and coordinating the design, verification, and evaluation of analog mixed-signal circuits in high-speed data communication ICs. The candidate will work closely with digital design, design verification, firmware, and analog design engineers to ensure that projects are completed on time and in high quality.

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What We're Looking For

Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-15 years of related professional experience.
Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.

Good personal communication skills and team working spirit.

Hardworking and motivated to be part of a highly competent design team.

Must be proficient in the following skills:

• Fundamental concepts in high-speed analog mixed-signal SerDes design

• Fundamental concepts in digital design, design verification, and timing closure

• Concepts in physical and layout design

• Excellent cross-discipline communication and interpersonal skills

• Ability to work independently and as part of a team

• Strong problem-solving and decision-making skills

Highly desirable skills:

• Experience with design flow and methodology

• Experience with silicon validation support

• Experience with power analysis and optimization

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Expected Base Pay Range (USD)

136,880 - 205,000, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .